Logic Synthesis and SOC Prototyping

Zusatztext

Emphasises SOC architecture and micro-architecture design with case studies Consists of the practical scenarios and issues and helpful to graduate students and professionals Covers SOC Design, implementation using VHDL, Synthesis and timing analysis Covers key case studies in the generic form for processor, buses, interfaces, memory controllers, DSP and Video controllers

Autorenportrait

Vaibbhav Taraate is Entrepreneur and Mentor at 1 Rupee S T. He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 years ofexperience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

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