Digital Logic Design Using Verilog

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Vaibbhav Taraate is Entrepreneur and Mentor at "Semiconductor Training @ Rs.1". He holds a BE (Electronics) degree from Shivaji University, Kohlapur in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his MTech (Aerospace Control and Guidance)  in 1999 from IIT Bombay. He has over 15 Years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.

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