Power Optimization in FPGA Routing circuits

Zusatztext

The work optimizes power in 4T,5T,6T,7T,8T,9T and 10T SRAM by comparing their configurations. Two mode based operations are proposed: Mode I operation and Mode-II operation. A 10T based SRAM write driver circuitry is proposed and comparison of Static Power, Static Power Dissipation, Performance metrics like Power delay product and Energy delay product are compared using TANNER 7.0. In future, Adiabatic logic work circuitry has to be implemented and results are to be obtained.

Autorenportrait

Dr Sundar Prakash Balaji acquired Doctorate from Anna University, Chennai. He owns Bachelor's and Master's degrees from Anna University, Chennai. He is currently working as Associate Professor, RVS Technical Campus - Coimbatore. His area of interests are not but limited to Low power VLSI Design, ASIC Design and Solid state devices.

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