SystemVerilog for Verification

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<P>SystemVerilog for Verification, Second Edition provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog 3.0 topics such as interfaces and data types.</P><P>This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch. This edition also includes a new chapter that covers Interfacing to C and many new and improved examples and explanations.</P><P>For hardware engineers, the book has several chapters with detailed explanations of Object Oriented Programming based on years of teaching OOP to hundreds of students. For software engineers, there is a wealth of information on testbenches, multithreaded code, and interfacing to hardware designs. The reader only needs to know the Verilog 1995 standard.</P><EM><P>"The complete book that covers verification concepts and use of system verilog in Verification, taking your from an easy start to advanced concepts with ease.</P><P>Paul D. Franzon, Alumni Distinguished Professor of ECE, North Carolina State University"</P></EM>

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